/*
 * linux/arch/arm/mach-omap3pe/mux.c
 *
 * Copyright (C) 2008-2009 Palm, Inc.
 *
 * Based on
 *
 * OMAP2 and OMAP3 pin multiplexing configurations
 *
 * Copyright (C) 2007 Texas Instruments Inc.
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#include <linux/module.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>

#include <asm/arch/control.h>
#include <asm/arch/mux.h>




struct pin_config omap34xx_pins[] = {
/*
 *		Name,				reg-offset, mux-mode | [active-mode | off-mode]
 */

/* SYS_CLKREQ */
MUX_CFG_34XX("AF25_SYS_CLKREQ_GPIO_1",		0xA06, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* SYS_OFF_MODE */
MUX_CFG_34XX("AF22_SYS_OFF_MODE_GPIO_9",	0xA18, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* McBSP1 */
MUX_CFG_34XX("W21_MCBSP1_CLKX_GPIO_162",	0x198, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("K26_MCBSP1_FSX_GPIO_161",		0x196, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U21_MCBSP1_DR_GPIO_159",		0x192, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

/* McBSP2 */
MUX_CFG_34XX("N21_MCBSP2_CLKX_GPIO_117",	0x13E, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("P21_MCBSP2_FSX_GPIO_116",		0x13C, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("R21_MCBSP2_DR_GPIO_118",		0x140, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("M21_MCBSP2_DX_GPIO_119",		0x142, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* McBSP3
 *    define the McBSP3 pins as input to keep them from driving the modem. Let
 *    the Triton drive the modem instead.  GPIO 140, 141, 142, 143
 */
MUX_CFG_34XX("AF6_3430_GPIO_140",		0x16c, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE6_3430_GPIO_141",		0x16e, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AF5_3430_GPIO_142",		0x170, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE5_3430_GPIO_143",		0x172, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
/* McBSP3 driven by OMAP */
MUX_CFG_34XX("AF6_3430_MCBSP3_DX",		0x16c, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE6_3430_MCBSP3_DR",		0x16e, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AF5_3430_MCBSP3_CLKX",		0x170, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE5_3430_MCBSP3_FSX",		0x172, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

/* McBSP5
 *    Define the McBSP5 pins as input to keep them from driving the modem. Let
 *    the Triton drive the modem instead.  GPIO 12, 18, 19, 20
 */
MUX_CFG_34XX("AF10_ETK_CLK_GPIO_12",		0x5d8, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AH9_ETK_D5_GPIO_19",		0x5e6, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AF13_ETK_D6_GPIO_20",		0x5e8, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE11_ETK_D4_GPIO_18",		0x5e4, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

/* USB */
/* UART active on USB */
MUX_CFG_34XX("T27_UART3_TX_IRTX",       0x1AA, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U28_UART3_RX_IRRX",       0x1AC, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U27_UART3_RTS_SD",        0x1AE, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U26_UART3_CTS_RCTX",      0x1B0, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
/* UART disabled on USB */
MUX_CFG_34XX("T27_HSUSB0_D0",			0x1AA, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U28_HSUSB0_D1",			0x1AC, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U27_HSUSB0_D2",			0x1AE, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U26_HSUSB0_D3",			0x1B0, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("U25_HSUSB0_D4",			0x1B2, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("V28_HSUSB0_D5",			0x1B4, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("V27_HSUSB0_D6",			0x1B6, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("V26_HSUSB0_D7",			0x1B8, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("T28_USB0HS_CLK",			0x1A2, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("T26_USB0HS_NXT",			0x1A8, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("T25_USB0HS_STP",			0x1A4, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("R28_USB0HS_DIR",			0x1A6, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

/* UART3 */
/* UART active on pads */
MUX_CFG_34XX("H20_3430_UART3_RX_IRRX",		0x19e, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("H21_3430_UART3_TX_IRTX",		0x1a0, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
/* UART disabled, not muxed */
MUX_CFG_34XX("H20_3430_GPIO165",		0x19e, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("H21_3430_GPIO166",		0x1a0, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)

/* Alternative configurations for SYS-nREQ pin */
MUX_CFG_34XX("AF26_SYS_NREQ",			0x1E0, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AF26_GPIO0",			0x1E0, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP | OMAP34XX_PIN_OFF_WAKEUPENABLE)

/* Touchscreen (SPI1) */
MUX_CFG_34XX("H18_3430_GPIO163_TP_RESET",	0x19a, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("H19_3430_GPIO164_TP_IRQ",		0x19c, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
/* NOTE for H19_3430_GPIO164_TP_IRQ:
 *   Need to pull down this line. Even though the TP PSoC is actively driving
 *   the line there is a window during power-up (and after OFF mode?) when the
 *   line is not driven. During this time we want the line to be low.
 */

MUX_CFG_34XX("AB3_3430_SPI1_CLK",		0x1C8, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AB4_3430_SPI1_O",			0x1CA, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA4_3430_SPI1_I",			0x1CC, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AC2_3430_SPI1_CS0",		0x1CE, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
MUX_CFG_34XX("AC2_3430_SPI1_CS0_OFF",		0x1CE, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
/* Touchscreen (SPI1) Programming Mode */
MUX_CFG_34XX("AB3_3430_SPI1_SCL",		0x1C8, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AB4_3430_SPI1_MOSI_MIRROR",	0x1CA, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AC2_3430_SPI1_SDA",		0x1CE, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

/* Charger Bypass */
MUX_CFG_34XX("V21_GPIO_158_CHG_BYPASS_EN",	0x190, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_HIGH)

/* LCD */
/* SPI3 */
MUX_CFG_34XX("H26_3430_LCD_SPI3_CLK",		0x100, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("H25_3430_LCD_SPI3_O",		0x102, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("E28_3430_LCD_SPI3_I",		0x104, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("J26_3430_LCD_SPI3_CS0",		0x106, OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("J26_3430_LCD_SPI3_CS0_OFF",	0x106, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

MUX_CFG_34XX("AG9_ETK_D9_GPIO_23",		0x5EE, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)

MUX_CFG_34XX("Y2_LCD_LED_PWM",			0x1D8, OMAP34XX_MUX_MODE1 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("Y2_LCD_LED_PWM_OFFMODE",		0x1D8, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)


/* MSECURE GPIO */
MUX_CFG_34XX("AF9_3430_MSECURE_GPIO",		0x5EC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* TLL FSUSB: FS TLL 3-pin & 2-pin mode for Port 1 */
MUX_CFG_34XX("AG12_3430_USB1FS_TLL_MM1_TXSE0",	0x5de, OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PD 10K */
MUX_CFG_34XX("AH12_3430_USB1FS_TLL_MM1_TXDAT",	0x5e0, OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K on VIO */

/* Modem Control */
MUX_CFG_34XX("AE1_3430_GPIO152", /* MWA */	0x184, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_WAKEUPENABLE)
MUX_CFG_34XX("AD1_3430_GPIO153", /* PWR */	0x186, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
#ifdef CONFIG_CORE_OFF
MUX_CFG_34XX("AD1_3430_GPIO153_PULLDOWN",	0x186, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AD1_3430_GPIO153_PULLUP",		0x186, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP   | OMAP34XX_PIN_OFF_NONE)
#endif
MUX_CFG_34XX("AD2_3430_GPIO154", /* BOOTM */	0x188, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("AC1_3430_GPIO155", /* MWAU */	0x18a, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_WAKEUPENABLE)
MUX_CFG_34XX("AA21_3430_GPIO157", /* AWM */	0x18e, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
#ifdef CONFIG_CORE_OFF
MUX_CFG_34XX("AA21_3430_GPIO157_PULLDOWN",	0x18e, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA21_3430_GPIO157_PULLUP",	0x18e, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP   | OMAP34XX_PIN_OFF_NONE)
#endif

/* UART1 */
MUX_CFG_34XX("AA8_3430_UART1_TX",		0x17c, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("AA9_3430_UART1_RTS",		0x17e, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA9_3430_UART1_GPIO",		0x17e, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("W8_3430_UART1_CTS",		0x180, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT  | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("Y8_3430_UART1_RX",		0x182, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT  | OMAP34XX_PIN_OFF_NONE | OMAP34XX_PIN_OFF_WAKEUPENABLE )

/* UART2 */ 
MUX_CFG_34XX("AB26_3430_UART2_CTS",		0x174, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT  | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AB25_3430_UART2_RTS",		0x176, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AB25_3430_UART2_GPIO",		0x176, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA25_3430_UART2_TX",		0x178, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("AD25_3430_UART2_RX",		0x17a, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT  | OMAP34XX_PIN_OFF_NONE | OMAP34XX_PIN_OFF_WAKEUPENABLE )

/* WiFi Pins */
MUX_CFG_34XX("AE2_WL_SD1_CLK",			0x158, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("AG5_WL_SD1_CMD",			0x15A, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K on WL-1.8-IO */
MUX_CFG_34XX("AH5_WL_SD1_D0",			0x15C, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on WL-1.8-IO */
MUX_CFG_34XX("AH4_WL_SD1_D1",			0x15E, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on WL-1.8-IO */
MUX_CFG_34XX("AG4_WL_SD1_D2",			0x160, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on WL-1.8-IO */
MUX_CFG_34XX("AF4_WL_SD1_D3",			0x162, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on WL-1.8-IO */

MUX_CFG_34XX("AF3_WL_IRQ",			0x168, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_WAKEUPENABLE )
MUX_CFG_34XX("AE3_WL_RST_nPWD",			0x16A, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
#ifdef CONFIG_CORE_OFF
MUX_CFG_34XX("AE3_WL_RST_nPWD_OFFMODE_HIGH",	0x16A, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP   | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE3_WL_RST_nPWD_OFFMODE_LOW",	0x16A, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
#endif

/* BT Pins */
MUX_CFG_34XX("AB1_BT_HOST_WAKE",		0x1D2, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_WAKEUPENABLE)
MUX_CFG_34XX("AB2_BT_nWAKE",			0x1D4, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
#ifdef CONFIG_CORE_OFF
MUX_CFG_34XX("AB2_BT_nWAKE_OFFMODE_HIGH",	0x1D4, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP   | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AB2_BT_nWAKE_OFFMODE_LOW",	0x1D4, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
#endif
MUX_CFG_34XX("AA3_BT_nRST",			0x1D6, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
#ifdef CONFIG_CORE_OFF
MUX_CFG_34XX("AA3_BT_nRST_OFFMODE_HIGH",	0x1D6, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLUP   | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA3_BT_nRST_OFFMODE_LOW",		0x1D6, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
#endif

/* Proximity Sensor Pins */
MUX_CFG_34XX("T8_3430_GPIO55",			0x0B6, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("R8_3430_GPIO56",			0x0B8, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_HIGH)
MUX_CFG_34XX("R8_3430_GPT10_PWM_EVT",		0x0B8, OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("V3_3430_GPT8_PWM_EVT",		0x1DE, OMAP34XX_MUX_MODE1 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* audio control */
MUX_CFG_34XX("AB18_3430_GPIO41",		0x088, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_HIGH)
MUX_CFG_34XX("AC19_3430_GPIO42",		0x08a, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_HIGH)
MUX_CFG_34XX("AB19_3430_GPIO43",		0x08c, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_HIGH)

/* POP-INT-1/2 */
MUX_CFG_34XX("P8_GP_NCS6_GPIO_57",		0x0BA, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("N8_GP_NCS7_GPIO_58",		0x0BC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE)


/* Gas Gauge */
MUX_CFG_34XX("J25_HDQ_SIO",			0x1C6, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 4.7K on VIO */

MUX_CFG_34XX("K21_I2C1_SCL",			0x1BA, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
MUX_CFG_34XX("J21_I2C1_SDA",			0x1BC, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
/* I2C2 Camera */
MUX_CFG_34XX("AF15_I2C2_SCL",			0x1BE, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
MUX_CFG_34XX("AE15_I2C2_SDA",			0x1C0, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
/* I2C3 Keypad */
MUX_CFG_34XX("AF14_I2C3_SCL",			0x1C2, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
MUX_CFG_34XX("AG14_I2C3_SDA",			0x1C4, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
/* SmartReflex */
MUX_CFG_34XX("AD26_I2C4_SCL",			0xA00, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */
MUX_CFG_34XX("AE26_I2C4_SDA",			0xA02, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 1.8K on VIO */

/* Keypad IRQ */
MUX_CFG_34XX("AE10_3430_GPIO13_KEY_INT",	0x5DA, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP | OMAP34XX_PIN_OFF_WAKEUPENABLE)

/* GPIO Keys */
MUX_CFG_34XX("AE13_3430_GPIO17_CORE_NAVI",	0x5E2, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AE7_3430_GPIO24_KEY_VOL_UP",	0x5F0, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("AF7_3430_GPIO25_KEY_VOL_DN",	0x5F2, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("AG7_3430_GPIO26_KEY_PTT",		0x5F4, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP | OMAP34XX_PIN_OFF_WAKEUPENABLE)
MUX_CFG_34XX("AH7_3430_GPIO27_SLIDER_OPEN",	0x5F6, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_INPUT_PULLUP | OMAP34XX_PIN_OFF_WAKEUPENABLE)
MUX_CFG_34XX("AG8_3430_GPIO28_RING",		0x5F8, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT | OMAP34XX_PIN_OFF_WAKEUPENABLE) /* has ext PU 180K on VIO */
MUX_CFG_34XX("AH8_3430_GPIO29_PWR_WIFI_KEY",	0x5FA, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT | OMAP34XX_PIN_OFF_WAKEUPENABLE) /* has ext PU */
MUX_CFG_34XX("AH3_3430_GPIO137_OPTICAL_SLIDER",	0x166, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE )

/* Headset detect */
MUX_CFG_34XX("B26_3430_GPIO111",		0x12E, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT | OMAP34XX_PIN_OFF_WAKEUPENABLE) /* has ext PU 100K on VIO */
/* Headset shutdown */
MUX_CFG_34XX("G25_3430_GPIO086",               0x0FC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("G25_3430_GPIO086_OFFMODE",       0x0FC, OMAP34XX_MUX_MODE7 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
/* Headset button PWM */
MUX_CFG_34XX("Y4_3430_MIC_ANS_ON",			0x1DC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* to wake up from suspend */
MUX_CFG_34XX("Y4_3430_MIC_ANS_OFF",			0x1DC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN) /* to wake up from suspend */
/* Headset button PWM interrupt */
MUX_CFG_34XX("H27_3430_GPIO087",		0x0FE, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP | OMAP34XX_PIN_OFF_WAKEUPENABLE)

/* TEMT6200 Light Sensor GPIO */
MUX_CFG_34XX("AF11_3430_GPIO14",		0x5DC, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* MAX8902A EN
 * GPIO99 and GPIO101 are physically connected. So we configure one pin as
 * output and the other pin as input.
 */
MUX_CFG_34XX("AG17_3430_GPIO99_CAM_PWD",	0x116, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("B24_3430_GPIO101_CAM_PWD",	0x11A, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)

/* CCP2 */
MUX_CFG_34XX("K28_3430_CSIB_CLKP",		0x122, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("L28_3430_CSIB_CLKN",		0x124, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("K27_3430_CSIB_DATP",		0x126, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)
MUX_CFG_34XX("L27_3430_CSIB_DATN",		0x128, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)

/*
 * tps6105x flash_sync
 * caution: gpio126 and gpio180 are tied together
 */
MUX_CFG_34XX("D25_3430_GPIO126",		0x132, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_OUTPUT_LOW)
MUX_CFG_34XX("Y3_3430_GPIO_180",		0x1DA, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)

/* Kionix Accelerometer */
MUX_CFG_34XX("T21_3430_GPIO160",		0x194, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)

/* MMC1 */
MUX_CFG_34XX("N28_MMC1_CLK",			0x144, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("M27_MMC1_CMD",			0x146, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K on VIO */
MUX_CFG_34XX("N27_MMC1_DAT0",			0x148, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
MUX_CFG_34XX("N26_MMC1_DAT1",			0x14A, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
MUX_CFG_34XX("N25_MMC1_DAT2",			0x14C, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
MUX_CFG_34XX("P28_MMC1_DAT3",			0x14E, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_NONE) /* has ext PU 100K on VIO */
MUX_CFG_34XX("P27_MMC1_DAT4",			0x150, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("P26_MMC1_DAT5",			0x152, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("R27_MMC1_DAT6",			0x154, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)
MUX_CFG_34XX("R25_MMC1_DAT7",			0x156, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT | OMAP34XX_PIN_OFF_INPUT_PULLUP)

#ifdef CONFIG_MACH_SIRLOIN
/* Boot mode pins */
MUX_CFG_34XX("AH26_SYS_BOOT0",			0xA0A, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has ext PD 10K */
MUX_CFG_34XX("AG26_SYS_BOOT1",			0xA0C, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K */
MUX_CFG_34XX("AE14_SYS_BOOT2",			0xA0E, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has ext PD 10K */
MUX_CFG_34XX("AF18_SYS_BOOT3",			0xA10, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has ext PD 10K */
MUX_CFG_34XX("AF19_SYS_BOOT4",			0xA12, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K */
MUX_CFG_34XX("AE21_SYS_BOOT5",			0xA14, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K */
MUX_CFG_34XX("AF21_SYS_BOOT6",			0xA16, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE) /* has ext PU 10K */

/* SYS_NRESWARM */
MUX_CFG_34XX("AF24_SYS_NRESWARM_GPIO_30",	0xA08, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP | OMAP34XX_PIN_OFF_NONE)

/* JTAG */
MUX_CFG_34XX("AA19_JTAG_TDO",			0xA50, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA17_JTAG_nTRST",			0xA1C, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has external PD 10K */
MUX_CFG_34XX("AA18_JTAG_TMS",			0xA20, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has external PD 10K */
MUX_CFG_34XX("AA20_JTAG_TDI",			0xA22, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA13_JTAG_TCK",			0xA1E, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_NONE) /* has external PD 10K */
MUX_CFG_34XX("AA12_JTAG_RTCK",			0xA4E, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA11_JTAG_EMU0",			0xA24, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)
MUX_CFG_34XX("AA10_JTAG_EMU1",			0xA26, OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_OFF_NONE)


// -wgr- MUX_CFG_34XX("",			0x000, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN | OMAP34XX_PIN_OFF_INPUT_PULLDOWN)

#endif

#define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)

};

static char *find_name(u16 addr)
{
	int i;

	for (i = 0; i < OMAP34XX_PINS_SZ; i++) {
		if (addr == omap34xx_pins[i].mux_reg) {
			return omap34xx_pins[i].name;
		}
	}
	return "not defined";
}

static void dump_range(u16 start, u16 end, u16 mask)
{
	u16 addr, val;

	for (addr = start; addr <= end; addr += 2) {
		val  = omap_ctrl_readw(addr);
		if( mask == 0 || (val & mask)) {
			char *name = find_name(addr);
			printk("IOPAD: %04x: %04x  (%s)\n", addr, val, name);
		}
	}
}


static int omap34xx_cfg_reg(const struct pin_config *cfg)
{
	static DEFINE_SPINLOCK(mux_spin_lock);
	unsigned long flags;
	u16 reg = 0;

	spin_lock_irqsave(&mux_spin_lock, flags);
	reg |= cfg->mux_val;
	omap_ctrl_writew(reg, cfg->mux_reg);
	spin_unlock_irqrestore(&mux_spin_lock, flags);

	return 0;
}

static struct omap_mux_cfg arch_mux_cfg = {
	.pins		= omap34xx_pins,
	.size		= OMAP34XX_PINS_SZ,
	.cfg_reg	= omap34xx_cfg_reg,
};

int __init omap3_mux_init(void)
{
	return omap_mux_register(&arch_mux_cfg);
}

